1. Field of the Invention
The present invention relates to a level-shifting pass gate.
2. Description of the Related Art
Such a gate may be embodied in the form of a metal-oxide-semiconductor (MOS) circuit for responding to input signals which are of substantially lower amplitude than the circuit supply voltage. Such circuits may be used in large-area silicon-on-insulator (SOI) circuits for interfacing with system signals of smaller voltage levels, typically in the region of 1.0 to 5.0 volts. Such circuits typically operate at significantly higher supply voltages, for example in the region of 10 to 20 volts. An example of this type of circuit is a monolithic driver for a flat-panel matrix display fabricated with poly-silicon thin-film transistors (TFTs).
FIG. 1 of the accompanying drawings illustrates a known type of level shifter as disclosed, for example, in U.S. Pat. No. 5,729,154. The circuit comprises an input stage formed by N-type MOS field effect transistors M1 and M3 and P-type field effect transistors M2 and M4. The output of this stage is connected to a conventional CMOS inverter comprising an N-type transistor M5 and a P-type transistor M6.
The gates of the transistors M2 and M4 are connected to a supply line vss so that these transistors operate substantially as resistors. The gate of the transistor M1 is connected to the gate and drain of the transistor M3, which therefore functions like a diode. The source of the transistor M3 is connected to receive a voltage Vbias which is between the voltages on the supply lines vss and vdd. The purpose of the transistor M3 is to provide a threshold voltage compensated bias voltage to the gate of the transistor M1. The source of the transistor M1 is connected to an input IN of the level shifter.
In use, the input IN receives a logic signal which switches between a lower or zero level Vss and an upper level VHH which is less than the supply voltage VDD on the supply line vdd. When the lower logic level VSS is supplied to the input IN, the gate-source voltage of the transistor M1 is large enough to ensure that the transistor M1 is turned on and the voltage of the drain is pulled down approximately to the voltage VSS of the supply line VSS. The inverter formed by the transistors M5 and M6 inverts this so that the inverted output OUTB rises substantially to the supply line potential VDD of the supply line vdd.
When the higher logic level VHH is applied to the input IN, the gate-source voltage of the transistor M1 is reduced such that the transistor M1 is only weakly conducting or is turned off. The transistor M2 thus pulls the input of the inverter towards the voltage VDD of the supply line vdd and above the switching point of the inverter M5, M6. The output OUTB of the inverter thus falls substantially to the voltage VSS of the supply line vss.
Although such an arrangement provides level-shifting of input high level logic signals, the level shifter of FIG. 1 presents a lower impedance input load to whatever signal line is connected to the input IN when the input signal is at the logic low level. Thus, when output signals from the level shifter are not required, any signal line connected to the input IN may be unacceptably loaded by the low input impedance of the level shifter to low level logic signals.
FIG. 2 of the accompanying drawings illustrates another known type of level shifter, for example as disclosed in EP 0 600 734 A. This level shifter differs from than shown in FIG. 1 of the accompanying drawings in that the source of the transistor M1 is connected to a complementary input INB whereas the source of the transistor M3 is connected to the direct input IN. Also, the gates of the transistors M2 and M4 are connected to the inputs IN and INB, respectively.
When the input IN receives the higher logic level VHH so that the complimentary input INB is at the lower input logic level VSS, the voltage at the gate of the transistor M1 is increased while the drive provided by the transistor M2 is reduced. Thus, the input of the inverter M5, M6 is lower than in the case of the level shifter shown in FIG. 1. Conversely, when the input IN receives the lower logic level VSS and the complimentary input INB receives the higher logic level VHH, the transistor M1 is turned harder off, thus allowing the input to the inverter M5, M6 to be higher than in the case of the level shifter shown in FIG. 1. This allows a greater degree of level shifting to be achieved while making the switching point of the inverter M5, M6 less critical. However, in this case, both inputs IN and INB are connected to the sources of the transistors M1 and M2, which present a low impedance load to any signal lines connected to the inputs.
FIG. 3 of the accompanying drawings illustrates a level shifter of the type disclosed, for example, in U.S. Pat. No. 5,748,026. Complementary inputs IN and INB are connected to the sources of diode-connected N-type transistors M3 and M3xe2x80x2, respectively, which are provided with load resistances in the form of conducting P-type transistors M4 and M4xe2x80x2. The bases and drains of the transistors M3 and M3xe2x80x2 are connected to the gates of N-type transistors M1 and M1xe2x80x2, respectively, which are provided with a current mirror load comprising P-type transistors M2 and M2xe2x80x2. The diode-connected transistors M3 and M3xe2x80x2 provide level shifting of the complementary input signals by adding a bias voltage. However, again, the inputs IN and INB present a low impedance load to the signal lines to which they are connected.
FIG. 4 of the accompanying drawings illustrates a simplified version of a known level shifter also disclosed in U.S. Pat. No. 5,748,026. This arrangement differs from that shown in FIG. 3 in that the transistors M3 and M3xe2x80x2 are of P-type and, in conjunction with the transistors M4 and M4xe2x80x2, are connected as source-followers whereas the sources of the transistors M1 and M1xe2x80x2 are connected to the inputs INB and IN. The transistors M3 and M3xe2x80x2 again provide initial level shifting of the input signals but, again, the inputs IN and INB are connected to transistor sources and so present a relatively low impedance load to signal lines connected to the inputs.
According to a first aspect of the invention, there is provided a level-shifting pass gate comprising: a first circuit comprising a pass transistor, whose main conduction path is connected between a signal input and a signal output, and a load connected to the signal output; and a second circuit have an enable input and being arranged to control the first circuit such that, when an enable signal supplied to the enable input is active and a first logic level is supplied to the signal input, the pass transistor provides a level-shifted logic level at the signal output and, when the enable signal is inactive, the signal input is set to a high impedance state and the signal output is set to a pre-determined state.
The pass transistor may be arranged to provide a substantially unshifted logic level at the signal output when the enable signal is active and a second logic level is supplied to the signal input. The first logic level may have a higher magnitude than the second logic level. The magnitude of the second logic level may be substantially equal to zero.
The second circuit may be arranged to switch off the first transistor when the enable signal is inactive.
The second circuit may be arranged to supply, to a control electrode of the pass transistor, a bias voltage greater than a threshold voltage of the pass transistor when the enable signal is active. The difference between the bias voltage and the first logic level may be less than the threshold voltage of the pass transistor.
The second circuit may comprise a bias voltage source comprising a resistance connected to an output electrode and a control electrode of a first transistor. The first transistor may have a common electrode connected to ground. As an alternative, the first transistor may have a common electrode connected to receive a high voltage level when the enable signal is in active and a low voltage level when the enable signal is inactive. As a further alternative, the first transistor may have a common electrode connected to a complementary signal input.
The common electrode of the first transistor may be connected via the main conduction path of a second transistor whose control electrode is arranged to receive a further bias voltage.
The resistance may comprise the main conduction path of a third transistor. The third transistor may be arranged to be switched off when the enable signal is inactive and to be conductive when the enable signal is active.
The control and output electrodes of the first transistor may be connected to a control electrode of the pass transistor.
The gate may comprise a fourth transistor arranged to connect a control electrode of the pass transistor to ground when the enable signal is inactive.
The gate may comprise of at least one further pass transistor, the or each of which has a main conduction path connected between a respective further signal input and the signal output.
The load may comprise a substantially fixed resistance and the predetermined state may comprise a high level state.
The load may comprise a load transistor of a conductivity type opposite that of the pass transistor. The pass transistor may have a higher drive capability than the load transistor.
The load transistor may be arranged to be switched off when the enable signal is inactive. The predetermined state may be a high impedance state. As an alternative, a pull-down transistor having a main conduction path connected between the signal output and ground may be arranged to be switched on when the enable signal is inactive and the predetermined state may be a low level state.
The load transistor may be arranged to receive a fixed bias and the predetermined state may be high level state. The load transistor may have a control electrode connected to receive a ground potential.
The signal output may be connected to the input of a first inverter. The gate may comprise a second controllable inverter whose input and output are connected to the output and input, respectively, of the first inverter and which is arranged to be enabled when the enable signal is inactive and to be disabled when the enable signal is active.
The or each transistor may comprise a field effect transistor. The gate may be embodied in a CMOS integrated circuit.
According to a second aspect of the invention, there is provided a driver circuit for a matrix display including a gate in accordance with a first aspect of the invention.
It is thus possible to provide a level-shifting pass gate which is very sensitive and which permits operation with very low voltage inputs. Such a gate has a high-operating speed which allows, for example, high speed shifting or sampling to be achieved. It is easy to implement a logic AND function for any number of low voltage inputs. A lower power consumption may be achieved because of improved logic level swings. The gate is robust to process variation and may be embodied by a relatively small number of transistors.
The pass gate incorporates an enabling or gating arrangement which allows the gate to be switched to a disabled state in which the output adopts a predetermined state irrespective of the input and the input presents a high impedance to signal lines connected to it. The predetermined states can be selected according to the following circuit requirements and can be in the form, for example, of a logic low level, a logic high level or a high impedance state. By switching the input to a high impedance state when the gate is disabled, unnecessary loading of the signal line connected to the input can be substantially avoided.